Previous, prior art Automated Test Equipment have attempted to measure high frequency signals, but the measurement of these high frequency signals has proven difficult. The results of the measurements when they have been obtained have often been unsatisfactory. One reason for the difficulty is related to the parasitic effects of the hardware fixturing of the prior art ATE equipment. Stray capacitance and inductance from the fixturing such as wafer probes, handler contactors and device sockets often have a detrimental effect on the high frequency electrical signals to be measured. Exemplary, the settling time of a palette digital to analog converter (DAC) could be difficult to accurately measure through a long wire since the inductance of this long wire would corrupt or affect the signal to be measured.
Matched impedance terminated coaxial cables have been used successfully in prior art ATE test fixtures to reduce the inductive and capacitive effects of the signal transmission path. A properly terminated coaxial cable appears as a purely resistive load to the device under test (DUT). Such terminated cables can only be successfully used to measure a signal if the device under test (DUT) is capable of driving the termination resistance without significantly affecting the signal under test. Typical ATE coaxial cables require a termination resistance of either fifty or ninety Ohms and as such require the DUT to drive a fifty or ninety Ohm resistive load. Many devices do not have such low impedance drive capability and as a consequence prior art ATE equipment cannot easily be used to measure high frequency electrical signals.
Measurements of these high frequency signals are also affected adversely by the limited speed of the A/D converters of the prior art. These prior art converters are adapted to operate at higher sampling rates which disadvantageously limits their voltage resolution. Exemplary, if a converter operates at a required sampling rate of 20 MHZ, the digitizer of the converter may have a resolution of only 12 bits instead of the preferred 16 to 24 bits common to lower frequency converters.
In certain prior art high speed digitizers, the stray inductance/capacitance and sampling resolution problems have been minimized by positioning a very high speed strobed comparator near the device under test (DUT). This comparator is used as a front-end to an undersampling successive approximation routine (SAR) A/D converter. Positioning the comparator near the DUT tends to minimize the effects of stray capacitance and inductance on the signal to be tested. FIG. 1 illustrates a prior art high speed digitizer including a SAR controller card and sampler head module. The sampler head includes a high bandwidth strobed comparator circuit positioned in an electrostatic metal can. The sampler head is positioned on the device interface board DIB near the device under test. The device under test is required to drive only the small input capacitance of the sampler head comparator plus a small amount of additional stray inductance/capacitance that is introduced by the signal path between the device under test and the sampler head. This provides a measurement circuit and signal path having a very high bandwidth. Additionally this measurement circuitry does not load the device under test with excess parasitic inductance and capacitance.
FIG. 2 illustrates a three-bit undersampled analog to digital A/D conversion of a sine wave which has been input to the sampler head. The broken line indicates the output of the SAR DAC which has been placed initially at its mid-scale voltage. At time=0, the one-bit result of a strobed comparison between the SAR DAC output voltage and the input sine wave is stored within the SAR logic and capture memory of FIG. 1. This bit corresponds to the most significant bit (MSB) of the first digitized sample. At a predetermined time after the capture of the first MSB, the output of the SAR DAC is raised to 1/2 full scale or lowered to -1/2 full scale, depending on the value of the previously determined MSB. At the first increment of time, the process is repeated to obtain another strobed comparison between the output of the SAR DAC and the input sine wave. Again, this second comparison result is stored in the SAR logic and capture memory of FIG. 1, along with the previously captured MSB. After the first increment of time, the output of the SAR DAC is again adjusted to reflect the first and second comparison results, continuing the successive approximation process in a binary search. At the second increment of time, the least significant bit of the first sample is obtained with a third strobed comparison and the SAR DAC output is returned to its mid-scale voltage. This completes the collection of the data for the first sample and the process is subsequently repeated for the second sample and the third sample, respectively. The strobed comparisons for each three-bit sample are taken at the same voltage point on the repeating input waveform. To sample different points on the input waveform, the strobed comparison timing for each three-bit sample must be offset from the strobe timing of the previous sample by a small time slip. The magnitude of time slip controls the high speed digitizer's effective sampling rate. Exemplary, a 100 ps time slip corresponds to a 10 GHz effective sampling rate. Although, FIG. 2 illustrates that the comparisons for each digitized sample are taken once per input waveform repetition period, it should be understood that the comparisons can be separated by any integer multiple of the input waveform repetition period to allow more settling time for the SAR DAC output.
The comparisons obtained from the comparator for the successive approximation routine are timed by employing a fixed frequency sampling clock combined with a swept delay circuit located in the prior art high speed digitizer. Because the SAR DAC operates at a relatively low frequency, a high resolution DAC can be chosen to increase the voltage resolution of the undersampling digitizer to sixteen or more bits.
The undersampling technique provides a high effective sampling rate, high resolution combination that would not be achievable using other prior art A/D converters. However, due to imperfections in the swept delay circuit, timing errors are introduced into the conversion of the analog signal. Three types of timing errors are common in the prior art digitizer: sweep range error, sweep linearity error, and timing jitter. Timing jitter results in increased noise in the digitized signal. Sweep linearity error produces distortion in the digitized signal. Sweep range error causes the time slip between samples to be either too large or too small, producing sampling rate error. Sampling rate error results in a digital signal that is incompatible for use with a non-windowed fast Fourier transform (FFT) mathematical routine. This aspect limits the desirability of using a swept delay circuit. More specifically, non-windowed FFT analysis is used extensively within the field of automatic test equipment to measure gain, distortion, signal to noise ratio, and many other common AC channel parameters. The inability to use non-windowed FFT analysis is a large disadvantage in the prior art.
The timing inaccuracies resulting from the swept delay generator result in a non-coherent sample set such as the one illustrated in FIG. 3. If an FFT is performed on the non-coherent data set, discontinuities such as those illustrated in FIG. 4 result from this transformation. The FFT routine attempts to interpret the non-repeating signal as a repeating one. Because the improperly interpreted signal contains a discontinuity corresponding to the endpoints of the sample set, non-windowed FFT analysis of the non-coherent sample set may result in significant measurement errors.
Thus, an important criterion of a captured digital signal is that it must be coherent to be compatible with non-windowed FFT analysis. The coherence requirement dictates that multiple copies of a digital signal sample set, placed end to end, must transition smoothly from the last sample in one copy to the first sample in the next. When the swept delay circuit is used in conjunction with undersampling techniques in prior art undersampling digitizers, the digital signals output from the digitizers are generally not coherent since timing of the swept signals are not well controlled. Although the waveform resulting from the swept delay undersampling digitizers are useful for time domain analysis such as rise time, fall time, and duty cycle, frequency domain analysis employing a non-windowed FFT is not reliable. Furthermore, timing jitter and sweep non-linearity errors of the swept delay undersampling digitizer increase the error in the sampling times which in turn adds distortion and noise.